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Design Requirements for Steeply Switching Logic Devices

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Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal $I_{rm on}/I_{rm off}$ and $E_{rm dyn}/E_{rm leak}$ ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state $S_{rm off}$, on -state $S_{rm on}$, and effective $S_{rm eff}$ inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal $E_{rm dyn}/E_{rm leak}$ ratio is approximately $(K/hbox{2})(S_{rm eff}/S_{rm off}) - hbox{0.56}(S_{rm on}/S_{rm off}) - hbox{0.56}$, where $K$ ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for $S_{rm off}$, $S_{rm on}$, and $S_{rm eff}$ are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope $S$ is insufficient, since energy diss-
pation is set mainly by $S_{rm eff}$ and not by $S$. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to $S_{rm on}/S_{rm off}$. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology.

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Design Requirements for Steeply Switching Logic Devices - 4.9 out of 5 based on 78 votes

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