A novel bias scheme is demonstrated for performance improvement of floating-body cell memory, particularly retention time. Its basic mechanism is based on carrier lifetime engineering, which takes advantage of generation lifetime that is longer than recombination lifetime. In addition, the proposed scheme is suitable for low-power operation; a high drain bias is unnecessary to generate excess carriers, which allows reliable endurance of up to $hbox{10}^{12}$ switching instances at 85 $^{circ}hbox{C}$.

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