In this paper, we present a new compact drain-current model for double-gate or triple-gate silicon on insulator (SOI) metal–oxide–semiconductor field-effect transistors, which is based on a physics-based 3-D analysis. Explicit analytical model equations for the height of the potential barrier are derived in closed form from a 3-D model for the channel electrostatics without the need to introduce any fitting parameter. The device current is described by a superposition of a surface-channel current above threshold and a center current in the subthreshold region, accounting for the movement of the most leaky path in the device cross section. Comparison with Technology Computer Aided Design (TCAD) shows a good scalability of the model down to a gate length of 30 nm. Furthermore, the $I$–$V$ characteristics are compared with measurements and obtain accurate results down to an effective channel length of 53 nm.

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