PROJECT TITLE :
Analysis of Degradation Mechanisms in Low-Temperature Polycrystalline Silicon Thin-Film Transistors under Dynamic Drain Stress
Degradation induced by dynamic drain stress in both n-type and p-type low-temperature polycrystalline silicon thin-film transistors (TFTs) is systematically investigated. A transition-time-dependent hot-carrier (HC) mechanism is attributed to be the dominant degradation mechanism even for stress amplitudes close to the operation condition. Previously proposed nonequilibrium-drain-junction degradation model is further elaborated by including time-dependent carrier emission/recombination process. Different from that of n-type TFTs, a two-stage degradation behavior is first observed in p-type TFTs. By considering the effect of electron trapping in the initial stage on the dynamic HC mechanism in the second stage, degradation of both n-type and p-type TFTs can be consistently understood within a unified model, which also explains the absence of the two-stage degradation in n-type TFTs. Finally, this paper is further extended to show that the unified model should also be applicable to HC degradation induced by dynamic gate stress.
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