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Top-Gate Staggered a-IGZO TFTs Adopting the Bilayer Gate Insulator for Driving AMOLED

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PROJECT TITLE :

Top-Gate Staggered a-IGZO TFTs Adopting the Bilayer Gate Insulator for Driving AMOLED

ABSTRACT:

We report the successful implementation of top-gate staggered amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) with decent performance and environmental stability by adopting the $hbox{SiO}_{x}/hbox{SiN}_{x}$ bilayer gate-insulator stack. The PECVD $hbox{SiO}_{x}$ and $ hbox{SiN}_{x}$ were used as the first and second gate insulators, respectively, in the TFT to simultaneously ensure the channel/gate-insulator interface properties for device performances and the water impermeability of the gate insulator for effective passivation of the channel layer. It was also found that the cleanliness of the back-channel interface (and thus the effectiveness of the source/drain etching process) is critical for the successful implementation of the top-gate staggered a-IGZO TFTs. In this paper, a two-step wet-etching process for source/drain was used to ensure the quality of the back-channel interface. Finally, we successfully integrated the top-gate staggered a-IGZO TFTs into a working 2.2-in active matrix organic light-emitting display panel, demonstrating the real use of the developed TFTs.


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Top-Gate Staggered a-IGZO TFTs Adopting the Bilayer Gate Insulator for Driving AMOLED - 4.7 out of 5 based on 68 votes

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