PROJECT TITLE :

A 1.92-Megapixel CMOS Image Sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs

ABSTRACT:

This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is $hbox{9} muhbox{m} times hbox{425} muhbox{m}$. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-$mu hbox{m}$ CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE: Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 ABSTRACT: A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin
PROJECT TITLE :A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line ArchitectureABSTRACT:A 3 MHz-to-1.eight GHz, 94 μW-to-nine.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology
PROJECT TITLE :Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked schemeABSTRACT:A brand new design scheme intended to boost the performance of true single-section clocked (TSPC) dual
PROJECT TITLE :Low-power, parasitic-insensitive interface circuit for capacitive microsensorsABSTRACT:Capacitive transduction is ubiquitously employed at macro- and particularly micro-scales because of their simple structure and
PROJECT TITLE: Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 ABSTRACT: A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry