Errors Limiting Split- Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs


The accuracy of the split-$CV$ mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a $hbox{Al}_{2}hbox{O}_{3}$ gate dielectric and an InP barrier, through a “simulated experiment” procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental $I$–$V$ and $CV$ curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split-$CV$ method can appreciably underestimate the actual channel mobility in these devices, with an error of $>$ 20% and $>$ 50% on peak mobility and high-$V_{GS}$ mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing $V_{GS}$. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-$CV$ mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.

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