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Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- Control Dielectrics

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PROJECT TITLE :

Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- Control Dielectrics

ABSTRACT:

In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler–Nordheim (FN)/FN mode and a good retention ($>$ 3 V after ten years) with small activation energy (0.35 eV up to 200 $^{circ}hbox{C}$), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices.


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Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- Control Dielectrics - 4.8 out of 5 based on 46 votes

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