A Novel Layout-Based Single Event Transient Injection Approach to Evaluate the Soft Error Rate of Large Combinational Circuits in Complimentary Metal-Oxide-Semiconductor Bulk Technology


As the technology scales down, area radiation induced soft errors are becoming a vital issue for the reliability of Integrated Circuits (ICs). In this paper, we have a tendency to propose a novel layout-based Single-Event Transient (SET) injection approach to guage the Soft Error Rate (SER) of enormous combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We contemplate the result of ion strike location on the SET pulse width in this approach. Significant-ion experiments on two different inverter chains are conducted to verify this layout-primarily based SET injection approach. The simulation and experiment results show that this approach can fairly mirror the SET pulse width distribution. Furthermore, we compare the soft error variety calculated by our proposed layout-based mostly approach with the conventional SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.

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