III–V Tunnel FET Model With Closed-Form Analytical Solution


Using an idealized semianalytical model of charge transport for InAs-primarily based tunneling FET, it is shown that the output and transfer characteristics will be accurately reproduced and could be used to develop compact models. The use of a mathematical approximation for the analytical resolution of the surface potential is vital here to minimize the computation time. The 20-nm gate homojunction and forty-nm gate heterojunction transistors have been simulated and compared with the calibrated numerical simulation results. The results are in smart agreement.

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