Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization


Thermal-constrained task scheduler for throughput optimization on 3-D multicore processors (three-D MCPs) has been studied extensively. But, these throughput-optimized strategies usually ignore energy consumption and overuse thermal simulations. So, during this transient, a brand new strategy named thermal-aware mapping and VoltagE scaling (TAMVES) is proposed to optimize throughput and energy consumption while satisfying thermal constraints (in terms of both peak temperature and temperature gradient) simultaneously. Layer-by-layer task-to-core mapping and thermal-and-energy-aware voltage scaling are incorporated in TAMVES to cut back peak temperature and temperature gradient while not intensive thermal simulation. Furthermore, idle time slots also are utilised by voltage scaling for minimizing energy consumption. Our experimental results show that underneath thermal constraints, TAMVES outperforms a previous work (3-D Wave) by 35.30p.c averagely on throughput. Additionally, TAMVES that features 3-order faster speed underneath timing constraints outperforms 3-D Wave for saving 51.17% more energy and reducing eight.thirty sevenp.c additional peak temperature and five.67p.c a lot of temperature gradient. Therefore, TAMVES has proven itself an effective task scheduler that optimizes throughput and energy on three-D MCPs beneath thermal constraints.

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