PROJECT TITLE :
Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization
We have a tendency to demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface lure density Dit below 2 × 1011 eV-1 · cm-two), n+-doping (active doping concentration Nact exceeding one × 1020 cm-three), and metallization (contact resistivity Pc below 2 × 10-seven Ω · cm2) modules. A brand new circular transmission line Pc extraction model that captures the parasitic metal resistance is proposed. At a offer voltage VDD of zero.5 V, forty-nm-gate-length FinFET devices achieved an ON-performance ION of 50 μA/μm at an OFF-state current IOFF of 100 nA/μm, a subthreshold swing Ssat of 124 mV/decade, and a peak transconductance gm of 310 μS/μm. The identical gate-stack and contacts were deployed on planar devices for comparison. Each FinFET and planar devices in this paper achieved the best reported gm/Ssat at VDD = zero.5 V so far and the shortest gate lengths for Ge nMOS enhancement-mode transistors.
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