PROJECT TITLE :
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling
The through-silicon-via (TSV) introduces new parasitic elements into 3-D ICs. This paper presents a completely unique technique of extracting the parasitic capacitance between TSVs and their surrounding wires. For the first time, we examine electrical field (E-field) sharing effects from multiple TSVs and neighboring wires and their impact on timing, power, and noise with full-chip sign-off analyses. For quick and correct full-chip extraction, we propose a pattern-matching algorithm that accounts for the physical dimensions of multiple TSVs and neighboring wires and captures all E-field interactions. Compared with the average error of a field solver, that of our extraction method, which requires solely 2.four s runtime and negligible memory for a full-chip sixty four-purpose quick Fourier rework (FFT64) style with 330 TSVs, is 0.063fF. Upon extraction of TSV-related parasitics, we observe that TSV-to-wire capacitance significantly increase average TSV net noise and therefore the longest path delay. To cut back TSV-to-wire coupling, we implement two full-chip optimization ways and show that increasing the minimum distance between TSVs and neighboring wires reduces each coupling noise and also the aggressor count. As a result of E-field sharing from grounded wire guard rings, victim TSVs are additional effectively shielded from aggressor noise. A full-chip analysis shows that these strategies are highly effective in reducing noise with solely slight impact on timing and space.
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