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A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

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A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes


Radiation-induced soft errors are a significant reliability concern for reminiscences. To ensure that memory contents don't seem to be corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they're often combined with interleaving. Interleaving, however, impacts memory style and performance and cannot perpetually be used in tiny recollections. This limitation has spurred interest in codes which will correct adjacent bit errors. In specific, many SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a value because it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this temporary, a new category of SEC-DED-DAEC codes springs from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The most disadvantage of the new codes is that they need a larger number of parity check bits. So, they will be useful when decoding delay or complexity is crucial or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with a number of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

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A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes - 4.9 out of 5 based on 24 votes

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