Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors


Vertical zinc oxide (ZnO) skinny-film transistors (TFTs) with submicrometer channel length have sensible performance, together with massive current density (>ten mA/mm), high mobility (> 14 cm $^2$ /Vs), and large current ON–OFF ratio ( $>10^7)$ . They also have uneven current–voltage ( $I$ – $V$ ) characteristics within the saturation region when the source and drain electrodes are interchanged. We have a tendency to have used two-D simulations with the Synopsis Sentaurus Device to model vertical ZnO TFTs. The devices studied in this paper had ZnO active layers deposited using spatial atomic layer deposition (SALD). Model parameters were calibrated by matching simulation results with experimental results of planar bottom-gate ZnO TFTs and further adjusted to fit vertical TFT (VTFT) experimental characteristics. We realize we tend to would like acceptor-like traps higher than and below the conduction band minimum to model the SALD ZnO semiconductor behavior; in this paper, we introduced these as bulk traps. We realize the uneven $I$ – $V$ characteristics arise from an ungated region close to the foot of the VTFT, and which incorporates a additional important result on charge injection than on charge extraction. Modeling TFTs with totally different ungated region lengths gave smart agreement with experimental characteristics.

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