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Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

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PROJECT TITLE :

Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

ABSTRACT:

By employing the linear increasing drift region width and the high-k dielectric region, a novel variation of lateral width (VLW) technique is proposed to even the equipotential contour and increase the drift doping concentration, which maximize the breakdown voltage and reduce the specific ON-resistance. The breakdown voltage exceeds 600 V on the VLW lateral double-diffused metal–oxide–semiconductor (LDMOS) with 1- $mu $ m silicon-on-insulator layer, 3- $mu $ m buried oxide, and 60- $mu $ m drift region length. The 3-D simulation indicates that the proposed device increases the breakdown voltage by 140%, while reduces the specific ON-resistance by 50% in comparison with the conventional (CONV) device with the same geometric parameters. Moreover, VLW LDMOS presents the best figure of merit, which is 10, 1.8, and 4.5 times higher than that of CONV, variation of lateral doping, and variation of lateral thickness devices, respectively.


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Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric - 4.8 out of 5 based on 49 votes

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