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Wafer-Level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs

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This letter demonstrates a new technology for the heterogeneous integration of GaN and Si devices, which is scalable at least up to 4-in wafers and compatible with conventional Si fabrication. The key step in the proposed technology is the fabrication of a Si (100)–GaN–Si hybrid wafer by bonding a silicon (100) on insulator (SOI) wafer to the nitride surface of an AlGaN/GaN on Si (111) wafer. A thin layer of silicon oxide is used to enhance the bonding between the SOI and the AlGaN/GaN wafers. Using this technology, Si pMOSFETs and GaN high-electron-mobility transistors have been fabricated on a 4-in hybrid wafer. Due to the high-temperature stability of GaN as well as the high-quality semiconductor material resulting from the transfer method, these devices exhibit excellent performance. A hybrid power amplifier has been fabricated as a circuit demonstrator, which shows the potential to integrate GaN and Si devices on the same chip to enable new performance in high-efficiency power amplifiers, mixed signal circuits, and digital electronics.

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Wafer-Level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs - 4.9 out of 5 based on 18 votes

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