This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality—wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current $( < hbox{5} hbox{pA}/muhbox{m})$ and high $I_{rm ON}/I_{rm OFF}$ ratio $(> hbox{10}^{6})$. Furthermore, we briefly discuss the implication of these devices in CMOS nand logic implementation.

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