The capacitive coupling interference within floating-gate transistors is the main scaling barrier for highly dense nand Flash memories. In this case study, we propose a simulation-based methodology for the variability modeling, which is caused by line edge roughness in advanced technological nodes. The aim of this work is to present the approach by modeling the threshold voltage disturbance propagation mechanism in a raw memory array, caused by the variability-affected parasitic coupling. The variability aware model is statistically designed for evaluation of the cell-to-cell interference variability impact on disturbances of threshold voltage and the error generation in a 16-nm half-pitch nand Flash memory.
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