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A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

1 1 1 1 1 Rating 4.80 (25 Votes)

ABSTRACT:

We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor $(C_{rm G})$ and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time $(t_{rm re} > hbox{5} hbox{s})$.


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A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration - 4.8 out of 5 based on 25 votes

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