Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration


The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for three-D integration on memory retention characteristics was electrically evaluated. A DRAM check chip was bonded to a Si interposer at three hundred $^circhboxC$ for two min and thinned right down to thirty-$muhboxm$ thickness. The DRAM cell characteristics, that show fifty% failure at 200 $muhboxs$, were not degraded from the packaged sample (prethinning) even once chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 $^circhboxC$. Meanwhile, the DRAM cell array shows 50percent failure at 70 $muhboxs$ once an intentional Cu diffusion from the backside surface for 30 min at 300 $^circ hboxC$. It means that that Cu atoms at the back surface reach the $ hboxSi-hboxSiO_2$ interface of the front surface in active areas and cause useful failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no vital change even when Cu diffusion. The on-current performance characterized by majority carriers is not an efficient criterion to characterize sensitively the Cu contamination impact.

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