The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering


The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called $V hboxth$ feedback). It is shown that the sense margin and the retention time will be kept constant versus the gate length by employing a positive back bias. Nevertheless, below a crucial $L$, there is no area for optimization, and therefore the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

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