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Self-Aligned Indium&#x2013;Gallium&#x2013;Zinc Oxide Thin-Film Transistor With Phosphorus-Doped Source/Drain Regions

PROJECT TITLE :

Self-Aligned Indium–Gallium–Zinc Oxide Thin-Film Transistor With Phosphorus-Doped Source/Drain Regions

ABSTRACT :

Self-aligned prime-gate amorphous indium–gallium–zinc oxide (a-IGZO) skinny-film transistors (TFTs) with phosphorus-doped source/drain regions are developed in this letter. The resulting a-IGZO TFT exhibits high thermal stability and smart electrical performance, together with field-result mobility of 5 $hboxcm^2/hboxVcdot hboxs$, a threshold voltage of 5.6 V, a subthreshold swing of zero.five V/dec, and an on/off current ratio of $ hbox6times hbox10^7$. With reducing of the channel length, smart characteristics are obtained with a small shift in the brink voltage and no degradation in the subthreshold swing.

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Improving graphene non-volatile memory using self-aligned gate

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Fabrication and Characterization of Gate-Last Self-Aligned AlN/GaN MISHEMTs With In Situ SiNx Gate Dielectric

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Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors

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Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

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Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

PROJECT TITLE :Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-OptimizationABSTRACT:Self-aligned double patterning (SADP) is being considered for use at the ten-nm technology node and below for routing

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