PROJECT TITLE :
Degradation and Full Recovery in High-Voltage Implanted-Gate SiC JFETs Subjected to Bipolar Current Stress
Electron–hole-recombination-induced stacking faults (SFs) are shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this letter, we tend to investigate the consequences of bipolar current stress on the electrical characteristics of ion-implanted gate vertical-channel JFETs with 100-$mu hboxm$ drift epilayers. JFETs are stressed at a fastened gate–drain dc bipolar current density of one hundred $hboxA/cm^2$ for five h. Many JFETs exhibit severe forward gate–drain voltage degradation, while others show intermediate or no degradation. As degradation below bipolar current stress is caused by basal plane dislocation (BPD)-induced SF formation and expansion, the variations in degradation severity are attributed to the nonuniform BPD concentrations in the JFETs' drift epitaxial layers. Forward/reverse gate–source, transfer, reverse gate–drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Forward gate–drain voltage and on-state conduction degrade in affected JFETs. The degradations are totally reversed by annealing at 350 $^circhboxC$ for ninety six h, while nondegraded electrical characteristics remain unaffected by the annealing. These results recommend that elevated-temperature bipolar JFET operation can proceed while not BPD-induced SF-related degradation. In the absence of BPDs, bipolar operation will not impact JFET electrical characteristics.
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