PROJECT TITLE :

Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

ABSTRACT :

During this letter, we investigate the impact of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the result of source–drain extension $(S/D_rm ext)$ scaling and device asymmetry on device and circuit performances for fifteen nm VNW CMOS. It's seen that, because of reduced series resistance, circuit delay continues to enhance with $S/D_rm ext$ down to ten nm, despite increased parasitic capacitances. Also, we have a tendency to show that asymmetry between prime and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by sixty five% with prime electrode as source, which is attributed to extend in series resistance and gate–drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40percent delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE :Massive Connectivity With Massive MIMO—Part I: Device Activity Detection and Channel Estimation - 2018ABSTRACT:This 2-half paper considers an uplink large device communication scenario in which a large number
PROJECT TITLE :On Uplink Virtual MIMO with Device Relaying Cooperation Enforcement in 5G Networks - 2018ABSTRACT:In this Project, a completely unique protocol is proposed in that mobile terminals (MT) kind a virtual Multiple-input
PROJECT TITLE :A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies - 2017ABSTRACT:Automatic synthesis of digital circuits has played a key role in obtaining high-performance styles. Whereas considerable
PROJECT TITLE : A Low Power Trainable Neuromorphic IntegratedCircuit That Is Tolerant to Device Mismatch - 2016 ABSTRACT: Random device mismatch that arises as a result of scaling of the CMOS (complementary metal-oxide semiconductor)
PROJECT TITLE : Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 ABSTRACT: A multilevel per cell (MLC) technique significantly improves

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry