Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform


During this letter, we investigate the impact of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the result of source–drain extension $(S/D_rm ext)$ scaling and device asymmetry on device and circuit performances for fifteen nm VNW CMOS. It's seen that, because of reduced series resistance, circuit delay continues to enhance with $S/D_rm ext$ down to ten nm, despite increased parasitic capacitances. Also, we have a tendency to show that asymmetry between prime and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by sixty five% with prime electrode as source, which is attributed to extend in series resistance and gate–drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40percent delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.

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