Ultralow Specific On-Resistance Superjunction Vertical DMOS With High- Dielectric Pillar


A superjunction (SJ) VDMOS with a high-$k$ (HK) dielectric pillar below the ditch gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only will increase the n-pillar doping concentration and thus reduces the particular on-resistance $(R_rm on, rm sp)$ but conjointly alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in an exceedingly high-voltage blocking state, resulting in an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to more scale back the $R_rm on, rm sp$. The $R_rm on, rm sp$ decreases by 42percent, and BV will increase by fifteenp.c compared with those of a typical SJ VDMOS.

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