Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application


A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including section-modification memory, has been presented. Per a diode array process scheme and technology computer-aided style (TCAD) simulation results, a quasi-physical model with a buried $ hboxn^+$ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a sixteen $ times$ 16 diode array shows a drive current density of $sim!! hbox56.6 hboxmA/muhboxm^2$, a BVD of $sim$8 V, a $J_rm on/J_rm off$ ratio of $sim!!hbox10^9$, and crosstalk immunity. Additionally, this calibrated physical model will be applied in the subsequent generation of silicon-based mostly fabrication with parameters extraction.

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