PROJECT TITLE :
Voltage Ramp Stress for Hot-Carrier Screening of Scaled CMOS Devices
The voltage ramp stress (VRS) methodology is introduced for hot-carrier screening of advanced CMOS devices. It is demonstrated that the voltage and the time dependence measured with VRS are in good agreement with the constant voltage stress procedure, yielding equivalent reliability modeling parameters for conventional poly-Si/SiON and metal-gate/high-$k$ n-channel MOSFETs. Since little knowledge about the transistor design is required for VRS testing, it becomes the preferred procedure for process screening and monitoring of advanced CMOS devices. Additionally, the VRS method is used to quantify channel hot-carrier degradation by correcting for bias temperature instability contributions during hot-carrier injection–VRS test.
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