Hybrid – and – Technique for Separate Extraction of Structure- and Bias-Dependent Parasitic Resistances in a-InGaZnO TFTs


We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances ($R_{S}$ and $R_{D}$) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, $C$– $V$ and $I$ –$V$ measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness $T_{rm IGZO}$, the gate length $L$, and the overlap length $L_{rm ov}$ between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component $R_{H}$ considering the transfer resistance $R_{rm LT}$ depending on the transfer length $L_{T}$ and the channel resistance $R_{rm CH}$, as well as the vertical components in the S/D $R_{rm VS}$ and $R_{rm VD}$. We confirmed the proposed technique through a separate extraction of $V_{GS}$ -independent contact-
resistances $(R_{rm CS}, R_{rm CD})$ from the channel length- and $V_{GS}$-dependent $R_{rm LT}$ and $R_{rm CH}$ .

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