An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS


This paper presents a network-on-chip (NoC) SerDes transceiver design for long distance interconnects in the mm range among MPSoCs. Its source synchronous clocking scheme enables application in GALS systems and allows utterly stoppable transceiver clocking for low idle power consumption. A capacitive line driver with combined resistive driver for well outlined DC swing is used and analyzed thoroughly by simulation studies. It is shown that correct DC swing definition is mandatory for strong operation of long links at high data rates. Prototypes of the transceiver over half-dozen mm bufferless on-chip interconnect are implemented in both 65 nm and twenty eight nm CMOS technologies. The sixty five nm realization achieves an efficiency of 173 fJ/bit/mm at 90 Gbit/s at one.twenty five V and 93 fJ/bit/mm at forty five Gbit/s low speed mode at zero.9 V. The twenty eight nm realization achieves 81 fJ/bit/mm at seventy two Gbit/s at 1.05 V and sixty four fJ/bit/mm at thirty six Gbit/s low speed mode at 0.ninety five V. The transceiver will be seamlessly integrated as black box point-to-point association into heterogeneous MPSoC NoCs to enable ultra-compact toplevel floorplan realization and increased energy potency. An example of a twenty-core MPSoC in 65 nm CMOS technology with ten serial NoC transceivers is presented.

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