PROJECT TITLE :
Pipelined CPU Design With FPGA in Teaching Computer Architecture
This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in an exceedingly computer design course. The class project is a five-stage pipelined thirty two-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set each one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, instead of having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS directions are enough to attain the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many a lot of students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project needs the implementation of a true CPU rather than utilizing simulators or just experimenting with prepared-made complete CPU models.
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