PROJECT TITLE :
Efficient Parallel Architecture for Linear Feedback Shift Registers
This temporary presents a replacement parallel architecture for linear feedback shift registers (LFSRs), that can be used to attain high-throughput Bose–Chaudhuri–Hocquenghem or cyclic redundancy check encoders for storage and communication systems. While previous parallel LFSR architectures have computed values by using the past input messages and therefore the register outputs, the proposed parallel architecture primarily based on the transposed serial LFSR calculates the output by using only the past feedback values. Thus, the proposed design reduces the realm–time product by up to 59% compared with the recent architecture.
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