On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems


The density of flash memory chips has doubled each two years in the past decade and also the trend is expected to continue. The increasing capacity of NAND flash memory ends up in giant RAM footprint on address mapping management. This paper proposes a completely unique Demand-based mostly block-level Address mapping theme with a two-level Caching mechanism (DAC) for giant-scale NAND flash storage systems. The objective is to reduce RAM footprint while not excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (referred to as the translation pages) within the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another 2 caches, the second-level cache is designed to cache selected translation pages. In such a way, both the foremost-frequently-accessed and sequentially accessed address mapping entries can be stored within the cache thus the cache hit ratio will be increased and therefore the system response time will be improved. To the best of our information, this is the primary work to scale back the RAM cost by using the demand-based mostly approach on block-level address mapping schemes. The experiments are conducted on a real embedded platform. The experimental results show that our technique can effectively cut back the RAM footprint while maintaining similar average system response time compared with previous work.

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