PROJECT TITLE :
Logic-I/O Threshold Comparing $gamma$-Dosimeter in Radiation Insensitive Deep-Sub-Micron CMOS
This paper discusses challenges of implementing embedded dosimeters into larger CMOS systems-on-chip (SoCs) in deep-scaled CMOS technologies (with gate lengths smaller than 90 nm) where the high level of intrinsic radiation hardness and restricted availability of floating gate structures prohibit realizing a highly sensitive radfet-type dosimeter. We tend to thus propose a completely unique Logic-I/O Threshold Comparison Dosimeter, which offers compatibility with advanced CMOS technology nodes and co-integration with different circuitry. The proposed dosimeter estimates dose level by directly comparing threshold voltages between I/O and logic devices. Furthermore, through fastidiously sizing the logic and i/O devices and designing the very important comparator circuitry, we will also achieve needed temperature independence for deep-area applications. A prototype is then fabricated in sixty five-nm CMOS, and measured up to seventy five Mrad(Si) of total ionized dose at a Cobalt 60 ( ) facility.
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