Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications


In an orthogonal frequency division multiplexing (OFDM)-primarily based digital transmitter, the inverse fast Fourier remodel (IFFT) processing unit consumes the foremost hardware area and power, especially as a result of of the twiddle multipliers in the Cooley-Tukey-based mostly decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications within the input stage of the IFFT unit and replaces them by the proposed 'pass-logic'. These replacements can be possible as a result of the inputs are bitwise with binary-part shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for eight to 128 points (N) were implemented with multipliers and 'pass-logics'. The performance enhancements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the overall power by vi.5p.c. The identical implementation on an ASIC, consumed twenty eightp.c less power and twenty sevenp.c lesser gates. In 128-purpose implementation, these PIs are more than those of the 64-purpose, therefore PI is in upward trend as N will increase. A chip for FFT processing as per IEEE 802.11a specifications (64-point, sixteen-bit knowledge) is intended with pass-logics, which uses twenty four 947 gates and consumes 6.45 mW at one.8 V, 20 MHz in zero.eighteen μm 1P6M CMOS process.

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