PROJECT TITLE :

Double-Sampling Design Paradigm—A Compendium of Architectures

ABSTRACT:

Aggressive technology scaling impacts dramatically parametric yield, life-span, and reliability of circuits fabricated in advanced nanometric nodes. These problems may become showstoppers when scaling deeper to the sub-10-nm domain. To mitigate them, varied approaches are proposed, as well as increasing guard bands, fault-tolerant style, and canary circuits. Every of them is subject to many of the following drawbacks: large area, power, or performance penalty; false positives; false negatives; and insufficient coverage of the failures encountered in the deep nanometric domain. This paper presents various double-sampling architectures, that permit mitigating all these failures at low area and performance penalties and conjointly enable important power reduction.