PROJECT TITLE :

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories

ABSTRACT:

Memristors are an attractive choice for use in future memory architectures but are vulnerable to high defect densities thanks to the nondeterministic nature of nanoscale fabrication. Many works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The flexibility of memristors to operate as an MLC permits for extremely dense, low-power recollections. Using a memristor as an MLC introduces fault mechanisms that can't occur in typical 2-level memory cells. During this paper, we develop fault models for memristor-based MLC crossbars. The standard approach to testing a memory subsystem entails testing one memory cell at a time. But, this testing strategy is time consuming and will not scale for dense, memristor reminiscences. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar recollections to check several memory cells simultaneously. During this paper, we tend to integrate solutions for detecting and locating faults in memristors. We tend to develop a power aware built-in self-test solution to detect these faults. We additionally propose a hybrid diagnosis theme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths throughout fault detection and diagnosis modes, whereas disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by twenty four.69p.c and twenty eightp.c, respectively, compared to traditional March tests.


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