Effective Search Point Reduction Algorithm and its VLSI Design for HDTV H.264/AVC Variable Block Size Motion Estimation


Variable block size motion estimation (VBSME) in H.264/AVC has greatly led to achieve an optimal inter frame encoding. But, the computation burden of the VBSME becomes the bottleneck of the H.264/AVC encoders. The conventional architecture in hardware realization is difficult to adopt a quick software algorithm appropriate to cut back the VBSME computation burden. Thus, this paper presents a probe purpose reduction (SPR) algorithm with an economical hardware design, ready to decrease the motion estimation time whereas maintaining the coding performance of H.264. The effectiveness of the proposed methodology is compared with those of existing methods with respect to chip area, operation frequency, and throughput rate. The proposed SPR algorithm will increase the coding speed by around 90%; with a peak signal-to-noise ratio drop of less than dB than that achieved by the JM reference software. The proposed SPR algorithm can operate at two hundred MHz with 191 k gate count, that supports high-definition television 1280$,times,$720 format.

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