PROJECT TITLE :
A Row-Parallel 8 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation
An algebraic integer (AI)-primarily based time-multiplexed row-parallel design and 2 final reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded a pair of-D discrete cosine transform (DCT). The architecture directly realizes a slip-free 2-D DCT while not using FRSs between row–column transforms, resulting in an 8$,times,$8 2-D DCT that's entirely freed from quantization errors in AI basis. Consequently, the user-selectable accuracy for each of the coefficients within the FRS facilitates every of the sixty four coefficients to own its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based mostly on: one) optimized Dempster–Macleod multipliers, and a couple of) expansion factor scaling. This architecture permits low-noise high-dynamic vary applications in digital video processing that needs full control of the finite-precision computation of the two-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on field-programmable gate array (FPGA) chip. Six designs, for four-bit and 8-bit input word sizes, using the 2 proposed FRS schemes, have been designed, simulated, physically implemented, and measured. The most clock rate and block rate achieved among eight-bit input styles are 307.787 MHz and 38.forty seven MHz, respectively, implying a pixel rate of $8times 307.787approx a pair of.462~rm GHz$ if eventually embedded during a real-time video-processing system. The equivalent frame rate is concerning 1187.35 Hz for the image size of 1920$,times,$1080. All implementations are purposeful on a Xilinx Virtex-half-dozen XC6VLX240T FPGA device.
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