Spike-Timing-Dependent Plasticity With Weight Dependence Evoked From Physical Constraints


Analogue and mixed-signal VLSI implementations of Spike-Timing-Dependent Plasticity (STDP) are reviewed. A circuit is presented with a compact implementation of STDP appropriate for parallel integration in massive synaptic arrays. In distinction to previously printed circuits, it uses the constraints of the silicon substrate to realize numerous forms and degrees of weight dependence of STDP. It conjointly uses reverse-biased transistors to scale back leakage from a capacitance representing weight. Chip results are presented showing: numerous ways that in that the learning rule may be shaped; how synaptic weights could retain some indication of their learned values over periods of minutes; and how distributions of weights for synapses convergent on single neurons could shift between a lot of or less extreme bimodality according to the strength of correlational cues in their inputs.

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