Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes


Recent trends in emerging nonvolatile memory systems necessitate economical read/write (R/W) schemes. Efficient solutions with zero sneak path current, nondestructive R/W operations, minimum space and low power are some of the key necessities. Toward this finish, we tend to propose a unique crossbar memory scheme employing a configuration row of cells for helping R/W operations. The proposed write scheme minimizes the overall power consumption compared to the previously proposed write schemes and reduces the state drift downside. We tend to conjointly propose two browse schemes, namely, assisted-restoring and self-resetting read. In assisted-restoring theme, we tend to use the configuration cells that are employed in the write theme, whereas we tend to implement further circuitry for self-reset that addresses the problem of destructive scan. Moreover, by formulating an analytical model of R/W operation, we have a tendency to compare the various schemes. The overhead for the proposed assisted-restoring write/browse scheme is an further redundant row for the given crossbar array. For a typical array size of $200times 200$ the realm overhead is regarding $0.5percent$, however, there's a 4X improvement in power consumption compared to the recently proposed write schemes. Quantitative analysis of the proposed scheme is analyzed by using simulation and analytical models.

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