Investigation of Single-Bit and Multiple-Bit Upsets in Oxide RRAM-Based 1T1R and Crossbar Memory Arrays
In this paper, the susceptibility of oxide-primarily based resistive switching random memory (RRAM) to heavy ion strikes is investigated. A physics-based mostly SPICE model calibrated with HfOx RRAM is used for circuit and array-level simulations. The RRAM state-flipping is attributed to the transient photocurrents at neighboring transistors. Single-bit-upset (SBU) caused by either single-event upset (SEU) or multiple-event upset (MEU) is modeled and simulated in the one-transistor and one-resistor (1T1R) array, which corroborates with experimental observations. Additionally, circuit simulation is performed to research the impact of transient-induced soft errors during a 1024 ×1024 crossbar array. The sensitive locations in crossbar arrays are the driver circuits at the edge of the array. The simulations show that the crossbar array with HfOx RRAM is of high radiation tolerance because of the V/2 bias scheme. But, multiple-bit upset (MBU) could occur if using other oxide materials with lower operation voltage. Voltage spikes generated at the sting of the array might propagate along rows or columns as there's no isolation between cells within the crossbar array.
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