High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures ABSTRACT: Based on previous three-step high-speed VLSI architecture for LFSR structures, this paper proposes an improved three-step LFSR architecture with both higher hardware efficiency and speed. Generator polynomials for the first and third steps are constructed with iterative small length polynomials, which can in turn be easily handled by proposed look-ahead pipelining algorithm. A new scheme is also proposed for cutting down the iteration bound of the LFSR structure in the second step. This architecture can be applied to any LFSR structure for high-speedparallel implementation. For example, for the parallel BCH (8191, 7684) encoder with different unfolding factors J from 8 to 32, the proposed design can achieve speedup of 2.83% to 15.78% and XOR gates savings of 9.67% to 26.28%. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Efficient FPGA implementation of convolution Implementation of a visible Watermarking in a secure still digital Camera using VLSI design
