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Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model - 2015


Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model - 2015


During this project we have a tendency to propose a straightforward setup time model for a transmission gate based mostly static latch, which we tend to later use to simplify customary cell library characterization methodology. We propose a straightforward model for the setup time which relates it linearly with input transition time (TR) and load capacitance (CL). We conjointly derive the region of validity of our model in the TR, CL house. We tend to derive the link of the model coefficients and also the model's region of validity with the dimensions of CMOS latch commonplace cell. We then derive easy expressions relating our model coefficients with the provision voltage, threshold voltage, and temperature variations. We have a tendency to use these relationships to simplify latch setup time characterization methodology, eliminating the requirement of about 67% HSPICE simulations. We have a tendency to show that our model and method of improving the characterization process are valid with the technology scaling and realistic input signals. We have a tendency to observe that the value of setup time obtained using our model based approach for latch characterization differ from their corresponding HSPICE based mostly technique by a most (average) of 3.a pair ofpercent (1.five%).

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