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High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis - 2015


High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis - 2015


The potential of active inductors (AIs) has been typically reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This project deals with these 2 open problems for a high-frequency CMOS AI characterized by high-quality issue, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a high-quality factor. In specific, it shows how, through an advanced little-signal circuit model, to carry out an accurate and reliable style at high frequency (over 10 GHz) in fashionable nanoscale CMOS method. The look methodology is validated through cases of study at 13 GHz implemented in a very commonplace ninety-nm CMOS process and characterised experimentally. The results show that the AI exhibits an equivalent inductance close to 3.2 nH with an associated quality factor close to 200. After, it reports a noise analysis. It shows that the AI exhibits a very low level of noise, enabling its application to the implementation of high-quality factor low-noise LC tank in high-frequency building blocks of radio frequency front-ends. The results show that the AI exhibits a noise power spectral density under -one hundred fifty dBm/Hz.

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