Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell - 2015 PROJECT TITLE: Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell - 2015 ABSTRACT: Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising different to conventional CMOS style due to the better electrostatic control and high mobility. The project presents a unique style of 10 Transistor ternary memory cell, with separate scan and write lines. Extensive HSPICE simulations have validated the scan-write functionality of the planning. Besides a vital reduction in transistor count, results show a minimum of forty fivepercent reduction in delay as compared to prevalent memory cell styles. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process - 2015 Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2015
